module pc_wrapper(
  input         clk,
  input         rst,
  input         we,
  input  [30:0] in_bundle,
  output [29:0] q
);

wire        branch;
wire [31:2] d;

assign {branch, d} = in_bundle;

pc u_pc(
  .clk(clk),
  .rst(rst),
  .we(we),
  .branch(branch),
  .d(d),
  .q(q)
);

endmodule
